main Project Status
Project File:	vga.xise	Parser Errors:
Module Name:	main	Implementation State:	New
Target Device:	xc6slx9-3tqg144	Errors:
Product Version:	ISE 13.1	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 12/02/2012 - 18:52:44