top_level Project Status (11/28/2012 - 20:21:40)
Project File: PVBline.xise Parser Errors: No Errors
Module Name: top_level Implementation State: Programming File Generated
Target Device: xc6slx9-3tqg144
  • Errors:
No Errors
Product Version:ISE 13.4
  • Warnings:
48 Warnings (5 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 198 11,440 1%  
    Number used as Flip Flops 198      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 359 5,720 6%  
    Number used as logic 354 5,720 6%  
        Number using O6 output only 169      
        Number using O5 output only 72      
        Number using O5 and O6 113      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 5      
        Number with same-slice register load 0      
        Number with same-slice carry load 5      
        Number with other load 0      
Number of occupied Slices 109 1,430 7%  
Nummber of MUXCYs used 204 2,860 7%  
Number of LUT Flip Flop pairs used 362      
    Number with an unused Flip Flop 168 362 46%  
    Number with an unused LUT 3 362 1%  
    Number of fully used LUT-FF pairs 191 362 52%  
    Number of unique control sets 10      
    Number of slice register sites lost
        to control set restrictions
26 11,440 1%  
Number of bonded IOBs 21 102 20%  
    Number of LOCed IOBs 21 21 100%  
    IOB Flip Flops 1      
Number of RAMB16BWERs 1 32 3%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 1 200 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.40      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Nov 29 01:32:38 2012048 Warnings (5 new)15 Infos (3 new)
Translation ReportCurrentThu Nov 29 01:32:44 2012001 Info (0 new)
Map ReportCurrentThu Nov 29 01:32:52 2012006 Infos (0 new)
Place and Route ReportCurrentThu Nov 29 01:33:00 2012000
Power Report     
Post-PAR Static Timing ReportCurrentThu Nov 29 01:33:04 2012003 Infos (0 new)
Bitgen ReportCurrentThu Nov 29 01:33:12 2012000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed Nov 28 19:49:54 2012
WebTalk ReportCurrentThu Nov 29 01:33:12 2012
WebTalk Log FileCurrentThu Nov 29 01:33:14 2012

Date Generated: 11/28/2012 - 15:30:00