********** Mapped Logic ********** |
$OpTx$FX_SC$436 <= ((NOT blk5 AND ram1 AND ram3 AND ram2)
OR (NOT blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2)); |
$OpTx$ram_sel/ram_sel_D2_INV$819 <= (ram1 AND ram3 AND ram2); |
bank(0) <= ((blk5_bank(0) AND $OpTx$FX_SC$436)
OR (ram_bank(0) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (blk1_bank(0) AND blk5 AND blk3 AND ram1 AND blk2 AND ram3 AND ram2) OR (blk2_bank(0) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2) OR (blk3_bank(0) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND ram3 AND ram2)); |
bank(1) <= ((blk5_bank(1) AND $OpTx$FX_SC$436)
OR (ram_bank(1) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (blk1_bank(1) AND blk5 AND blk3 AND ram1 AND blk2 AND ram3 AND ram2) OR (blk2_bank(1) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2) OR (blk3_bank(1) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND ram3 AND ram2)); |
bank(2) <= ((blk5_bank(2) AND $OpTx$FX_SC$436)
OR (ram_bank(2) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (blk1_bank(2) AND blk5 AND blk3 AND ram1 AND blk2 AND ram3 AND ram2) OR (blk2_bank(2) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2) OR (blk3_bank(2) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND ram3 AND ram2)); |
bank(3) <= ((blk5_bank(3) AND $OpTx$FX_SC$436)
OR (ram_bank(3) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (blk1_bank(3) AND blk5 AND blk3 AND ram1 AND blk2 AND ram3 AND ram2) OR (blk2_bank(3) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2) OR (blk3_bank(3) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND ram3 AND ram2)); |
bank(4) <= ((blk5_bank(4) AND $OpTx$FX_SC$436)
OR (ram_bank(4) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (blk1_bank(4) AND blk5 AND blk3 AND ram1 AND blk2 AND ram3 AND ram2) OR (blk2_bank(4) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2) OR (blk3_bank(4) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND ram3 AND ram2)); |
bank(5) <= ((blk5_bank(5) AND $OpTx$FX_SC$436)
OR (ram_bank(5) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (blk1_bank(5) AND blk5 AND blk3 AND ram1 AND blk2 AND ram3 AND ram2) OR (blk2_bank(5) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2) OR (blk3_bank(5) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND ram3 AND ram2)); |
bank(6) <= ((blk5_bank(6) AND $OpTx$FX_SC$436)
OR (ram_bank(6) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (blk1_bank(6) AND blk5 AND blk3 AND ram1 AND blk2 AND ram3 AND ram2) OR (blk2_bank(6) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2) OR (blk3_bank(6) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND ram3 AND ram2)); |
FDCPE_blk1_bank0: FDCPE port map (blk1_bank(0),data(0).PIN,NOT clock,blk1_bank_CLR(0),'0',blk1_bank_CE(0));
blk1_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en); blk1_bank_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk1_bank1: FDCPE port map (blk1_bank(1),data(1).PIN,NOT clock,blk1_bank_CLR(1),'0',blk1_bank_CE(1));
blk1_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en); blk1_bank_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk1_bank2: FDCPE port map (blk1_bank(2),data(2).PIN,NOT clock,blk1_bank_CLR(2),'0',blk1_bank_CE(2));
blk1_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en); blk1_bank_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk1_bank3: FDCPE port map (blk1_bank(3),data(3).PIN,NOT clock,blk1_bank_CLR(3),'0',blk1_bank_CE(3));
blk1_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en); blk1_bank_CE(3) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk1_bank4: FDCPE port map (blk1_bank(4),data(4).PIN,NOT clock,blk1_bank_CLR(4),'0',blk1_bank_CE(4));
blk1_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en); blk1_bank_CE(4) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk1_bank5: FDCPE port map (blk1_bank(5),data(5).PIN,NOT clock,blk1_bank_CLR(5),'0',blk1_bank_CE(5));
blk1_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en); blk1_bank_CE(5) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk1_bank6: FDCPE port map (blk1_bank(6),data(6).PIN,NOT clock,blk1_bank_CLR(6),'0',blk1_bank_CE(6));
blk1_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en); blk1_bank_CE(6) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk2_bank0: FDCPE port map (blk2_bank(0),data(0).PIN,NOT clock,blk2_bank_CLR(0),'0',blk2_bank_CE(0));
blk2_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en); blk2_bank_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk2_bank1: FDCPE port map (blk2_bank(1),data(1).PIN,NOT clock,blk2_bank_CLR(1),'0',blk2_bank_CE(1));
blk2_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en); blk2_bank_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk2_bank2: FDCPE port map (blk2_bank(2),data(2).PIN,NOT clock,blk2_bank_CLR(2),'0',blk2_bank_CE(2));
blk2_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en); blk2_bank_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk2_bank3: FDCPE port map (blk2_bank(3),data(3).PIN,NOT clock,blk2_bank_CLR(3),'0',blk2_bank_CE(3));
blk2_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en); blk2_bank_CE(3) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk2_bank4: FDCPE port map (blk2_bank(4),data(4).PIN,NOT clock,blk2_bank_CLR(4),'0',blk2_bank_CE(4));
blk2_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en); blk2_bank_CE(4) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk2_bank5: FDCPE port map (blk2_bank(5),data(5).PIN,NOT clock,blk2_bank_CLR(5),'0',blk2_bank_CE(5));
blk2_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en); blk2_bank_CE(5) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk2_bank6: FDCPE port map (blk2_bank(6),data(6).PIN,NOT clock,blk2_bank_CLR(6),'0',blk2_bank_CE(6));
blk2_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en); blk2_bank_CE(6) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk3_bank0: FDCPE port map (blk3_bank(0),data(0).PIN,NOT clock,blk3_bank_CLR(0),'0',blk3_bank_CE(0));
blk3_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en); blk3_bank_CE(0) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk3_bank1: FDCPE port map (blk3_bank(1),data(1).PIN,NOT clock,blk3_bank_CLR(1),'0',blk3_bank_CE(1));
blk3_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en); blk3_bank_CE(1) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk3_bank2: FDCPE port map (blk3_bank(2),data(2).PIN,NOT clock,blk3_bank_CLR(2),'0',blk3_bank_CE(2));
blk3_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en); blk3_bank_CE(2) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk3_bank3: FDCPE port map (blk3_bank(3),data(3).PIN,NOT clock,blk3_bank_CLR(3),'0',blk3_bank_CE(3));
blk3_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en); blk3_bank_CE(3) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk3_bank4: FDCPE port map (blk3_bank(4),data(4).PIN,NOT clock,blk3_bank_CLR(4),'0',blk3_bank_CE(4));
blk3_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en); blk3_bank_CE(4) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk3_bank5: FDCPE port map (blk3_bank(5),data(5).PIN,NOT clock,blk3_bank_CLR(5),'0',blk3_bank_CE(5));
blk3_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en); blk3_bank_CE(5) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk3_bank6: FDCPE port map (blk3_bank(6),data(6).PIN,NOT clock,blk3_bank_CLR(6),'0',blk3_bank_CE(6));
blk3_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en); blk3_bank_CE(6) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk5_bank0: FDCPE port map (blk5_bank(0),data(0).PIN,NOT clock,blk5_bank_CLR(0),'0',blk5_bank_CE(0));
blk5_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en); blk5_bank_CE(0) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk5_bank1: FDCPE port map (blk5_bank(1),data(1).PIN,NOT clock,blk5_bank_CLR(1),'0',blk5_bank_CE(1));
blk5_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en); blk5_bank_CE(1) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk5_bank2: FDCPE port map (blk5_bank(2),data(2).PIN,NOT clock,blk5_bank_CLR(2),'0',blk5_bank_CE(2));
blk5_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en); blk5_bank_CE(2) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk5_bank3: FDCPE port map (blk5_bank(3),data(3).PIN,NOT clock,blk5_bank_CLR(3),'0',blk5_bank_CE(3));
blk5_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en); blk5_bank_CE(3) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk5_bank4: FDCPE port map (blk5_bank(4),data(4).PIN,NOT clock,blk5_bank_CLR(4),'0',blk5_bank_CE(4));
blk5_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en); blk5_bank_CE(4) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk5_bank5: FDCPE port map (blk5_bank(5),data(5).PIN,NOT clock,blk5_bank_CLR(5),'0',blk5_bank_CE(5));
blk5_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en); blk5_bank_CE(5) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_blk5_bank6: FDCPE port map (blk5_bank(6),data(6).PIN,NOT clock,blk5_bank_CLR(6),'0',blk5_bank_CE(6));
blk5_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en); blk5_bank_CE(6) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND address(2)); |
FDCPE_cart_config10: FDCPE port map (cart_config1(0),data(0).PIN,NOT clock,cart_config1_CLR(0),'0',cart_config1_CE(0));
cart_config1_CLR(0) <= (NOT reset.PIN AND NOT reset_en); cart_config1_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config11: FDCPE port map (cart_config1(1),data(1).PIN,NOT clock,cart_config1_CLR(1),'0',cart_config1_CE(1));
cart_config1_CLR(1) <= (NOT reset.PIN AND NOT reset_en); cart_config1_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config12: FDCPE port map (cart_config1(2),data(2).PIN,NOT clock,cart_config1_CLR(2),'0',cart_config1_CE(2));
cart_config1_CLR(2) <= (NOT reset.PIN AND NOT reset_en); cart_config1_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config20: FDCPE port map (cart_config2(0),data(0).PIN,NOT clock,'0',cart_config2_PRE(0),cart_config2_CE(0));
cart_config2_PRE(0) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config21: FDCPE port map (cart_config2(1),data(1).PIN,NOT clock,cart_config2_CLR(1),'0',cart_config2_CE(1));
cart_config2_CLR(1) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config22: FDCPE port map (cart_config2(2),data(2).PIN,NOT clock,cart_config2_CLR(2),'0',cart_config2_CE(2));
cart_config2_CLR(2) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config23: FDCPE port map (cart_config2(3),data(3).PIN,NOT clock,cart_config2_CLR(3),'0',cart_config2_CE(3));
cart_config2_CLR(3) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(3) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config24: FDCPE port map (cart_config2(4),data(4).PIN,NOT clock,cart_config2_CLR(4),'0',cart_config2_CE(4));
cart_config2_CLR(4) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(4) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config25: FDCPE port map (cart_config2(5),data(5).PIN,NOT clock,cart_config2_CLR(5),'0',cart_config2_CE(5));
cart_config2_CLR(5) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(5) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config26: FDCPE port map (cart_config2(6),data(6).PIN,NOT clock,cart_config2_CLR(6),'0',cart_config2_CE(6));
cart_config2_CLR(6) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(6) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_cart_config27: FDCPE port map (cart_config2(7),data(7).PIN,NOT clock,cart_config2_CLR(7),'0',cart_config2_CE(7));
cart_config2_CLR(7) <= (NOT reset.PIN AND NOT reset_en); cart_config2_CE(7) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
data_I(0) <= ((EXP6_.EXP)
OR ($OpTx$ram_sel/ram_sel_D2_INV$819.EXP) OR (address(1) AND address(0) AND blk5_bank(0) AND address(2)) OR (NOT address(1) AND address(0) AND blk2_bank(0) AND address(2)) OR (NOT address(1) AND NOT address(0) AND cart_config1(0) AND NOT address(2)) OR (NOT address(1) AND NOT address(0) AND blk1_bank(0) AND address(2))); data(0) <= data_I(0) when data_OE(0) = '1' else 'Z'; data_OE(0) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
data_I(1) <= ((ram_bank(1).EXP)
OR (blk1_bank(1).EXP) OR (address(1) AND address(0) AND blk5_bank(1) AND address(2)) OR (NOT address(1) AND address(0) AND blk2_bank(1) AND address(2)) OR (NOT address(1) AND NOT address(0) AND cart_config1(1) AND NOT address(2)) OR (NOT address(1) AND NOT address(0) AND blk1_bank(1) AND address(2))); data(1) <= data_I(1) when data_OE(1) = '1' else 'Z'; data_OE(1) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
data_I(2) <= ((cart_config2(1).EXP)
OR (cart_config1(1).EXP) OR (address(1) AND address(0) AND ram_bank(2) AND NOT address(2)) OR (address(1) AND NOT address(0) AND blk3_bank(2) AND address(2)) OR (NOT address(1) AND address(0) AND cart_config2(2) AND NOT address(2)) OR (NOT address(1) AND address(0) AND blk2_bank(2) AND address(2))); data(2) <= data_I(2) when data_OE(2) = '1' else 'Z'; data_OE(2) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
data_I(3) <= ((blk5_bank(2).EXP)
OR (address(1) AND address(0) AND ram_bank(3) AND NOT address(2)) OR (address(1) AND NOT address(0) AND blk3_bank(3) AND address(2)) OR (NOT address(1) AND address(0) AND cart_config2(3) AND NOT address(2)) OR (NOT address(1) AND address(0) AND blk2_bank(3) AND address(2))); data(3) <= data_I(3) when data_OE(3) = '1' else 'Z'; data_OE(3) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
data_I(4) <= ((blk5_bank(1).EXP)
OR (address(1) AND address(0) AND ram_bank(4) AND NOT address(2)) OR (address(1) AND NOT address(0) AND blk3_bank(4) AND address(2)) OR (NOT address(1) AND address(0) AND cart_config2(4) AND NOT address(2)) OR (NOT address(1) AND address(0) AND blk2_bank(4) AND address(2))); data(4) <= data_I(4) when data_OE(4) = '1' else 'Z'; data_OE(4) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
data_I(5) <= ((blk3_bank(2).EXP)
OR (address(1) AND address(0) AND ram_bank(5) AND NOT address(2)) OR (address(1) AND NOT address(0) AND blk3_bank(5) AND address(2)) OR (NOT address(1) AND address(0) AND cart_config2(5) AND NOT address(2)) OR (NOT address(1) AND address(0) AND blk2_bank(5) AND address(2))); data(5) <= data_I(5) when data_OE(5) = '1' else 'Z'; data_OE(5) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
data_I(6) <= ((ram_bank(6).EXP)
OR (ram_bank(5).EXP) OR (address(1) AND address(0) AND ram_bank(6) AND NOT address(2)) OR (address(1) AND NOT address(0) AND blk3_bank(6) AND address(2)) OR (NOT address(1) AND address(0) AND cart_config2(6) AND NOT address(2)) OR (NOT address(1) AND address(0) AND blk2_bank(6) AND address(2))); data(6) <= data_I(6) when data_OE(6) = '1' else 'Z'; data_OE(6) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
data_I(7) <= (NOT address(1) AND address(0) AND cart_config2(7) AND
NOT address(2)); data(7) <= data_I(7) when data_OE(7) = '1' else 'Z'; data_OE(7) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6)); |
flash_ce <= NOT (((cart_config1(0) AND NOT cart_config1(1) AND
NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (cart_config2(0) AND NOT cart_config2(1) AND NOT blk1) OR (cart_config2(2) AND NOT cart_config2(3) AND NOT blk2) OR (cart_config2(4) AND NOT cart_config2(5) AND NOT blk3) OR (cart_config2(6) AND NOT cart_config2(7) AND NOT blk5))); |
oe <= NOT ((r_w AND cart_en)); |
FDCPE_ram_bank0: FDCPE port map (ram_bank(0),data(0).PIN,NOT clock,ram_bank_CLR(0),'0',ram_bank_CE(0));
ram_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en); ram_bank_CE(0) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_ram_bank1: FDCPE port map (ram_bank(1),data(1).PIN,NOT clock,ram_bank_CLR(1),'0',ram_bank_CE(1));
ram_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en); ram_bank_CE(1) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_ram_bank2: FDCPE port map (ram_bank(2),data(2).PIN,NOT clock,ram_bank_CLR(2),'0',ram_bank_CE(2));
ram_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en); ram_bank_CE(2) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_ram_bank3: FDCPE port map (ram_bank(3),data(3).PIN,NOT clock,ram_bank_CLR(3),'0',ram_bank_CE(3));
ram_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en); ram_bank_CE(3) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_ram_bank4: FDCPE port map (ram_bank(4),data(4).PIN,NOT clock,ram_bank_CLR(4),'0',ram_bank_CE(4));
ram_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en); ram_bank_CE(4) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_ram_bank5: FDCPE port map (ram_bank(5),data(5).PIN,NOT clock,ram_bank_CLR(5),'0',ram_bank_CE(5));
ram_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en); ram_bank_CE(5) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
FDCPE_ram_bank6: FDCPE port map (ram_bank(6),data(6).PIN,NOT clock,ram_bank_CLR(6),'0',ram_bank_CE(6));
ram_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en); ram_bank_CE(6) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
ram_ce <= NOT (((cart_config1(1) AND
NOT $OpTx$ram_sel/ram_sel_D2_INV$819) OR (cart_config2(1) AND NOT blk1) OR (cart_config2(3) AND NOT blk2) OR (cart_config2(5) AND NOT blk3) OR (cart_config2(7) AND NOT blk5))); |
reset_I <= '0';
reset <= reset_I when reset_OE = '1' else 'Z'; reset_OE <= reset_en; |
FDCPE_reset_en: FDCPE port map (reset_en,reset_en_D,NOT clock,'0','0');
reset_en_D <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND data(7).PIN AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND NOT address(2)); |
we <= ((r_w)
OR (NOT cart_en) OR (NOT cart_config1(0) AND NOT cart_config2(0) AND NOT cart_config2(2) AND NOT cart_config2(4) AND NOT cart_config2(6))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |