cpldfit:  version K.39                              Xilinx Inc.
                                  Fitter Report
Design Name: UltiMem                             Date:  2-23-2014,  4:49PM
Device Used: XC9572XL-5-TQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
69 /72  ( 96%) 245 /360  ( 68%) 181/216 ( 84%)   47 /72  ( 65%) 41 /72  ( 57%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          18/18*      51/54       72/90       8/18
FB2          18/18*      27/54       56/90      11/18
FB3          16/18       52/54       56/90       7/18
FB4          17/18       51/54       61/90      15/18
             -----       -----       -----      -----    
             69/72      181/216     245/360     41/72 

* - Resource is exhausted

** Global Control Resources **

Signal 'clock' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   20          20    |  I/O              :    40      66
Output        :   11          11    |  GCK/IO           :     1       3
Bidirectional :    9           9    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     41          41

** Power Data **

There are 69 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 20 Outputs **

Signal                            Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                              Pts   Inps          No.  Type    Use     Mode Rate State
data<1>                           8     22    FB1_1   16   I/O     I/O     STD  FAST 
data<2>                           7     21    FB1_4   20   I/O     I/O     STD  FAST 
data<3>                           7     21    FB1_6   15   I/O     I/O     STD  FAST 
data<4>                           7     21    FB1_8   17   I/O     I/O     STD  FAST 
data<5>                           7     21    FB1_10  28   I/O     I/O     STD  FAST 
data<7>                           2     16    FB1_13  36   I/O     I/O     STD  FAST 
oe                                1     2     FB1_16  39   I/O     O       STD  FAST 
data<6>                           7     21    FB2_3   91   I/O     I/O     STD  FAST 
reset                             1     1     FB3_1   41   I/O     I/O     STD  FAST 
bank<5>                           5     13    FB3_2   32   I/O     O       STD  FAST 
data<0>                           8     22    FB3_5   35   I/O     I/O     STD  FAST 
bank<6>                           5     13    FB3_8   37   I/O     O       STD  FAST 
flash_ce                          5     15    FB3_11  52   I/O     O       STD  FAST 
ram_ce                            5     10    FB3_14  55   I/O     O       STD  FAST 
we                                3     7     FB3_16  64   I/O     O       STD  FAST 
bank<0>                           5     13    FB4_2   67   I/O     O       STD  FAST 
bank<1>                           5     13    FB4_5   68   I/O     O       STD  FAST 
bank<2>                           5     13    FB4_9   66   I/O     O       STD  FAST 
bank<3>                           5     13    FB4_13  85   I/O     O       STD  FAST 
bank<4>                           5     13    FB4_17  90   I/O     O       STD  FAST 

** 49 Buried Nodes **

Signal                            Total Total Loc     Pwr  Reg Init
Name                              Pts   Inps          Mode State
ram_bank<1>                       3     17    FB1_2   STD  RESET
cart_config2<1>                   3     17    FB1_3   STD  RESET
cart_config1<1>                   3     17    FB1_5   STD  RESET
blk5_bank<2>                      3     17    FB1_7   STD  RESET
blk5_bank<1>                      3     17    FB1_9   STD  RESET
blk3_bank<2>                      3     17    FB1_11  STD  RESET
blk3_bank<1>                      3     17    FB1_12  STD  RESET
blk2_bank<2>                      3     17    FB1_14  STD  RESET
blk2_bank<1>                      3     17    FB1_15  STD  RESET
blk1_bank<2>                      3     17    FB1_17  STD  RESET
blk1_bank<1>                      3     17    FB1_18  STD  RESET
reset_en                          1     15    FB2_1   STD  RESET
ram_bank<6>                       3     17    FB2_2   STD  RESET
ram_bank<5>                       3     17    FB2_4   STD  RESET
ram_bank<2>                       3     17    FB2_5   STD  RESET
cart_config2<7>                   3     17    FB2_6   STD  RESET
cart_config2<6>                   3     17    FB2_7   STD  RESET
cart_config2<5>                   3     17    FB2_8   STD  RESET
cart_config2<2>                   3     17    FB2_9   STD  RESET
cart_config1<2>                   3     17    FB2_10  STD  RESET
blk5_bank<6>                      3     17    FB2_11  STD  RESET
blk5_bank<5>                      3     17    FB2_12  STD  RESET
blk3_bank<6>                      3     17    FB2_13  STD  RESET
blk3_bank<5>                      3     17    FB2_14  STD  RESET
blk2_bank<6>                      3     17    FB2_15  STD  RESET
blk2_bank<5>                      3     17    FB2_16  STD  RESET
blk1_bank<6>                      3     17    FB2_17  STD  RESET
blk1_bank<5>                      3     17    FB2_18  STD  RESET
$OpTx$ram_sel/ram_sel_D2_INV$819  1     3     FB3_6   STD  
$OpTx$FX_SC$436                   2     6     FB3_7   STD  
ram_bank<0>                       3     17    FB3_9   STD  RESET
cart_config2<0>                   3     17    FB3_10  STD  RESET
cart_config1<0>                   3     17    FB3_12  STD  RESET
blk5_bank<0>                      3     17    FB3_13  STD  RESET
blk3_bank<0>                      3     17    FB3_15  STD  RESET
blk2_bank<0>                      3     17    FB3_17  STD  RESET
blk1_bank<0>                      3     17    FB3_18  STD  RESET
ram_bank<4>                       3     17    FB4_3   STD  RESET
ram_bank<3>                       3     17    FB4_4   STD  RESET
cart_config2<4>                   3     17    FB4_6   STD  RESET

Signal                            Total Total Loc     Pwr  Reg Init
Name                              Pts   Inps          Mode State
cart_config2<3>                   3     17    FB4_7   STD  RESET
blk5_bank<4>                      3     17    FB4_8   STD  RESET
blk5_bank<3>                      3     17    FB4_10  STD  RESET
blk3_bank<4>                      3     17    FB4_11  STD  RESET
blk3_bank<3>                      3     17    FB4_12  STD  RESET
blk2_bank<4>                      3     17    FB4_14  STD  RESET
blk2_bank<3>                      3     17    FB4_15  STD  RESET
blk1_bank<4>                      3     17    FB4_16  STD  RESET
blk1_bank<3>                      3     17    FB4_18  STD  RESET

** 21 Inputs **

Signal                            Loc     Pin  Pin     Pin     
Name                                      No.  Type    Use     
clock                             FB1_9   22~  GCK/I/O GCK/I
address<3>                        FB2_1   87   I/O     I
address<4>                        FB2_2   94   I/O     I
address<2>                        FB2_4   93   I/O     I
address<6>                        FB2_5   95   I/O     I
address<7>                        FB2_6   96   I/O     I
address<9>                        FB2_8   97   I/O     I
blk3                              FB2_10  1    I/O     I
r_w                               FB2_12  6    I/O     I
ram2                              FB2_13  8    I/O     I
address<0>                        FB2_18  92   I/O     I
ram3                              FB4_4   72   I/O     I
io                                FB4_6   76   I/O     I
cart_en                           FB4_7   77   I/O     I
blk1                              FB4_10  81   I/O     I
ram1                              FB4_11  74   I/O     I
address<8>                        FB4_12  82   I/O     I
blk5                              FB4_14  78   I/O     I
address<1>                        FB4_15  89   I/O     I
address<5>                        FB4_16  86   I/O     I
blk2                              FB4_18  79   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               51/3
Number of signals used by logic mapping into function block:  51
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
data<1>               8       3<-   0   0     FB1_1   16    I/O     I/O
ram_bank<1>           3       0   /\1   1     FB1_2   13    I/O     (b)
cart_config2<1>       3       0   \/1   1     FB1_3   18    I/O     (b)
data<2>               7       2<-   0   0     FB1_4   20    I/O     I/O
cart_config1<1>       3       0   /\1   1     FB1_5   14    I/O     (b)
data<3>               7       2<-   0   0     FB1_6   15    I/O     I/O
blk5_bank<2>          3       0   /\2   0     FB1_7   25    I/O     (b)
data<4>               7       2<-   0   0     FB1_8   17    I/O     I/O
blk5_bank<1>          3       0   /\2   0     FB1_9   22    GCK/I/O GCK/I
data<5>               7       2<-   0   0     FB1_10  28    I/O     I/O
blk3_bank<2>          3       0   /\2   0     FB1_11  23    GCK/I/O (b)
blk3_bank<1>          3       0     0   2     FB1_12  33    I/O     (b)
data<7>               2       0     0   3     FB1_13  36    I/O     I/O
blk2_bank<2>          3       0     0   2     FB1_14  27    GCK/I/O (b)
blk2_bank<1>          3       0     0   2     FB1_15  29    I/O     (b)
oe                    1       0     0   4     FB1_16  39    I/O     O
blk1_bank<2>          3       0     0   2     FB1_17  30    I/O     (b)
blk1_bank<1>          3       0   \/2   0     FB1_18  40    I/O     (b)

Signals Used by Logic in Function Block
  1: reset.PIN         18: blk1_bank<5>      35: cart_config1<2> 
  2: data<2>.PIN       19: blk2_bank<1>      36: cart_config2<1> 
  3: data<1>.PIN       20: blk2_bank<2>      37: cart_config2<2> 
  4: address<0>        21: blk2_bank<3>      38: cart_config2<3> 
  5: address<1>        22: blk2_bank<4>      39: cart_config2<4> 
  6: address<2>        23: blk2_bank<5>      40: cart_config2<5> 
  7: address<3>        24: blk3_bank<1>      41: cart_config2<7> 
  8: address<4>        25: blk3_bank<2>      42: cart_en 
  9: address<5>        26: blk3_bank<3>      43: clock 
 10: address<6>        27: blk3_bank<4>      44: io 
 11: address<7>        28: blk3_bank<5>      45: r_w 
 12: address<8>        29: blk5_bank<1>      46: ram_bank<1> 
 13: address<9>        30: blk5_bank<2>      47: ram_bank<2> 
 14: blk1_bank<1>      31: blk5_bank<3>      48: ram_bank<3> 
 15: blk1_bank<2>      32: blk5_bank<4>      49: ram_bank<4> 
 16: blk1_bank<3>      33: blk5_bank<5>      50: ram_bank<5> 
 17: blk1_bank<4>      34: cart_config1<1>   51: reset_en 

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
data<1>              ...XXXXXXXXXXX....X....X....X....XXX.....XXXXX.............. 22
ram_bank<1>          X.XXXXXXXXXXX.....................X......X.XX.....X......... 17
cart_config2<1>      X.XXXXXXXXXXX.....................X......X.XX.....X......... 17
data<2>              ...XXXXXXXXXX.X....X....X....X....X.X....XXXX.X............. 21
cart_config1<1>      X.XXXXXXXXXXX.....................X......X.XX.....X......... 17
data<3>              ...XXXXXXXXXX..X....X....X....X...X..X...XXXX..X............ 21
blk5_bank<2>         XX.XXXXXXXXXX.....................X......X.XX.....X......... 17
data<4>              ...XXXXXXXXXX...X....X....X....X..X...X..XXXX...X........... 21
blk5_bank<1>         X.XXXXXXXXXXX.....................X......X.XX.....X......... 17
data<5>              ...XXXXXXXXXX....X....X....X....X.X....X.XXXX....X.......... 21
blk3_bank<2>         XX.XXXXXXXXXX.....................X......X.XX.....X......... 17
blk3_bank<1>         X.XXXXXXXXXXX.....................X......X.XX.....X......... 17
data<7>              ...XXXXXXXXXX.....................X.....XXXXX............... 16
blk2_bank<2>         XX.XXXXXXXXXX.....................X......X.XX.....X......... 17
blk2_bank<1>         X.XXXXXXXXXXX.....................X......X.XX.....X......... 17
oe                   .........................................X..X............... 2
blk1_bank<2>         XX.XXXXXXXXXX.....................X......X.XX.....X......... 17
blk1_bank<1>         X.XXXXXXXXXXX.....................X......X.XX.....X......... 17
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               27/27
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
reset_en              1       0     0   4     FB2_1   87    I/O     I
ram_bank<6>           3       0   \/1   1     FB2_2   94    I/O     I
data<6>               7       2<-   0   0     FB2_3   91    I/O     I/O
ram_bank<5>           3       0   /\1   1     FB2_4   93    I/O     I
ram_bank<2>           3       0     0   2     FB2_5   95    I/O     I
cart_config2<7>       3       0     0   2     FB2_6   96    I/O     I
cart_config2<6>       3       0     0   2     FB2_7   3     GTS/I/O (b)
cart_config2<5>       3       0     0   2     FB2_8   97    I/O     I
cart_config2<2>       3       0     0   2     FB2_9   99    GSR/I/O (b)
cart_config1<2>       3       0     0   2     FB2_10  1     I/O     I
blk5_bank<6>          3       0     0   2     FB2_11  4     GTS/I/O (b)
blk5_bank<5>          3       0     0   2     FB2_12  6     I/O     I
blk3_bank<6>          3       0     0   2     FB2_13  8     I/O     I
blk3_bank<5>          3       0     0   2     FB2_14  9     I/O     (b)
blk2_bank<6>          3       0     0   2     FB2_15  11    I/O     (b)
blk2_bank<5>          3       0     0   2     FB2_16  10    I/O     (b)
blk1_bank<6>          3       0     0   2     FB2_17  12    I/O     (b)
blk1_bank<5>          3       0     0   2     FB2_18  92    I/O     I

Signals Used by Logic in Function Block
  1: reset.PIN         10: address<4>        19: blk5_bank<6> 
  2: data<7>.PIN       11: address<5>        20: cart_config1<2> 
  3: data<6>.PIN       12: address<6>        21: cart_config2<6> 
  4: data<5>.PIN       13: address<7>        22: cart_en 
  5: data<2>.PIN       14: address<8>        23: clock 
  6: address<0>        15: address<9>        24: io 
  7: address<1>        16: blk1_bank<6>      25: r_w 
  8: address<2>        17: blk2_bank<6>      26: ram_bank<6> 
  9: address<3>        18: blk3_bank<6>      27: reset_en 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
reset_en             .X...XXXXXXXXXX....X.X.XX............... 15
ram_bank<6>          X.X..XXXXXXXXXX....X.X.XX.X............. 17
data<6>              .....XXXXXXXXXXXXXXXXXXXXX.............. 21
ram_bank<5>          X..X.XXXXXXXXXX....X.X.XX.X............. 17
ram_bank<2>          X...XXXXXXXXXXX....X.X.XX.X............. 17
cart_config2<7>      XX...XXXXXXXXXX....X.X.XX.X............. 17
cart_config2<6>      X.X..XXXXXXXXXX....X.X.XX.X............. 17
cart_config2<5>      X..X.XXXXXXXXXX....X.X.XX.X............. 17
cart_config2<2>      X...XXXXXXXXXXX....X.X.XX.X............. 17
cart_config1<2>      X...XXXXXXXXXXX....X.X.XX.X............. 17
blk5_bank<6>         X.X..XXXXXXXXXX....X.X.XX.X............. 17
blk5_bank<5>         X..X.XXXXXXXXXX....X.X.XX.X............. 17
blk3_bank<6>         X.X..XXXXXXXXXX....X.X.XX.X............. 17
blk3_bank<5>         X..X.XXXXXXXXXX....X.X.XX.X............. 17
blk2_bank<6>         X.X..XXXXXXXXXX....X.X.XX.X............. 17
blk2_bank<5>         X..X.XXXXXXXXXX....X.X.XX.X............. 17
blk1_bank<6>         X.X..XXXXXXXXXX....X.X.XX.X............. 17
blk1_bank<5>         X..X.XXXXXXXXXX....X.X.XX.X............. 17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               52/2
Number of signals used by logic mapping into function block:  52
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
reset                 1       0     0   4     FB3_1   41    I/O     I/O
bank<5>               5       0     0   0     FB3_2   32    I/O     O
(unused)              0       0     0   5     FB3_3   49    I/O     
(unused)              0       0   \/2   3     FB3_4   50    I/O     (b)
data<0>               8       3<-   0   0     FB3_5   35    I/O     I/O
$OpTx$ram_sel/ram_sel_D2_INV$819
                      1       0   /\1   3     FB3_6   53    I/O     (b)
$OpTx$FX_SC$436       2       0     0   3     FB3_7   54    I/O     (b)
bank<6>               5       0     0   0     FB3_8   37    I/O     O
ram_bank<0>           3       0     0   2     FB3_9   42    I/O     (b)
cart_config2<0>       3       0     0   2     FB3_10  60    I/O     (b)
flash_ce              5       0     0   0     FB3_11  52    I/O     O
cart_config1<0>       3       0     0   2     FB3_12  61    I/O     (b)
blk5_bank<0>          3       0     0   2     FB3_13  63    I/O     (b)
ram_ce                5       0     0   0     FB3_14  55    I/O     O
blk3_bank<0>          3       0     0   2     FB3_15  56    I/O     (b)
we                    3       0     0   2     FB3_16  64    I/O     O
blk2_bank<0>          3       0     0   2     FB3_17  58    I/O     (b)
blk1_bank<0>          3       0     0   2     FB3_18  59    I/O     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_SC$436                   19: blk2              36: cart_config2<2> 
  2: $OpTx$ram_sel/ram_sel_D2_INV$819  20: blk2_bank<0>      37: cart_config2<3> 
  3: reset.PIN                         21: blk2_bank<5>      38: cart_config2<4> 
  4: data<0>.PIN                       22: blk2_bank<6>      39: cart_config2<5> 
  5: address<0>                        23: blk3              40: cart_config2<6> 
  6: address<1>                        24: blk3_bank<0>      41: cart_config2<7> 
  7: address<2>                        25: blk3_bank<5>      42: cart_en 
  8: address<3>                        26: blk3_bank<6>      43: clock 
  9: address<4>                        27: blk5              44: io 
 10: address<5>                        28: blk5_bank<0>      45: r_w 
 11: address<6>                        29: blk5_bank<5>      46: ram1 
 12: address<7>                        30: blk5_bank<6>      47: ram2 
 13: address<8>                        31: cart_config1<0>   48: ram3 
 14: address<9>                        32: cart_config1<1>   49: ram_bank<0> 
 15: blk1                              33: cart_config1<2>   50: ram_bank<5> 
 16: blk1_bank<0>                      34: cart_config2<0>   51: ram_bank<6> 
 17: blk1_bank<5>                      35: cart_config2<1>   52: reset_en 
 18: blk1_bank<6>                     

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
reset                ...................................................X........ 1
bank<5>              XX..............X.X.X.X.X.X.X................XXX.X.......... 13
data<0>              ....XXXXXXXXXX.X...X...X...X..X.XX.......XXXX...X........... 22
$OpTx$ram_sel/ram_sel_D2_INV$819 
                     .............................................XXX............ 3
$OpTx$FX_SC$436      ..................X...X...X..................XXX............ 6
bank<6>              XX...............XX..XX..XX..X...............XXX..X......... 13
ram_bank<0>          ..XXXXXXXXXXXX..................X........X.XX......X........ 17
cart_config2<0>      ..XXXXXXXXXXXX..................X........X.XX......X........ 17
flash_ce             .X............X...X...X...X...XX.XXXXXXXX................... 15
cart_config1<0>      ..XXXXXXXXXXXX..................X........X.XX......X........ 17
blk5_bank<0>         ..XXXXXXXXXXXX..................X........X.XX......X........ 17
ram_ce               .X............X...X...X...X....X..X.X.X.X................... 10
blk3_bank<0>         ..XXXXXXXXXXXX..................X........X.XX......X........ 17
we                   ..............................X..X.X.X.X.X..X............... 7
blk2_bank<0>         ..XXXXXXXXXXXX..................X........X.XX......X........ 17
blk1_bank<0>         ..XXXXXXXXXXXX..................X........X.XX......X........ 17
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               51/3
Number of signals used by logic mapping into function block:  51
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1   65    I/O     
bank<0>               5       0     0   0     FB4_2   67    I/O     O
ram_bank<4>           3       0     0   2     FB4_3   71    I/O     (b)
ram_bank<3>           3       0     0   2     FB4_4   72    I/O     I
bank<1>               5       0     0   0     FB4_5   68    I/O     O
cart_config2<4>       3       0     0   2     FB4_6   76    I/O     I
cart_config2<3>       3       0     0   2     FB4_7   77    I/O     I
blk5_bank<4>          3       0     0   2     FB4_8   70    I/O     (b)
bank<2>               5       0     0   0     FB4_9   66    I/O     O
blk5_bank<3>          3       0     0   2     FB4_10  81    I/O     I
blk3_bank<4>          3       0     0   2     FB4_11  74    I/O     I
blk3_bank<3>          3       0     0   2     FB4_12  82    I/O     I
bank<3>               5       0     0   0     FB4_13  85    I/O     O
blk2_bank<4>          3       0     0   2     FB4_14  78    I/O     I
blk2_bank<3>          3       0     0   2     FB4_15  89    I/O     I
blk1_bank<4>          3       0     0   2     FB4_16  86    I/O     I
bank<4>               5       0     0   0     FB4_17  90    I/O     O
blk1_bank<3>          3       0     0   2     FB4_18  79    I/O     I

Signals Used by Logic in Function Block
  1: $OpTx$FX_SC$436                   18: blk1_bank<2>      35: blk5_bank<1> 
  2: $OpTx$ram_sel/ram_sel_D2_INV$819  19: blk1_bank<3>      36: blk5_bank<2> 
  3: reset.PIN                         20: blk1_bank<4>      37: blk5_bank<3> 
  4: data<4>.PIN                       21: blk2              38: blk5_bank<4> 
  5: data<3>.PIN                       22: blk2_bank<0>      39: cart_config1<2> 
  6: address<0>                        23: blk2_bank<1>      40: cart_en 
  7: address<1>                        24: blk2_bank<2>      41: io 
  8: address<2>                        25: blk2_bank<3>      42: r_w 
  9: address<3>                        26: blk2_bank<4>      43: ram1 
 10: address<4>                        27: blk3              44: ram2 
 11: address<5>                        28: blk3_bank<0>      45: ram3 
 12: address<6>                        29: blk3_bank<1>      46: ram_bank<0> 
 13: address<7>                        30: blk3_bank<2>      47: ram_bank<1> 
 14: address<8>                        31: blk3_bank<3>      48: ram_bank<2> 
 15: address<9>                        32: blk3_bank<4>      49: ram_bank<3> 
 16: blk1_bank<0>                      33: blk5              50: ram_bank<4> 
 17: blk1_bank<1>                      34: blk5_bank<0>      51: reset_en 

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
bank<0>              XX.............X....XX....XX....XX........XXXX.............. 13
ram_bank<4>          ..XX.XXXXXXXXXX.......................XXXX........X......... 17
ram_bank<3>          ..X.XXXXXXXXXXX.......................XXXX........X......... 17
bank<1>              XX..............X...X.X...X.X...X.X.......XXX.X............. 13
cart_config2<4>      ..XX.XXXXXXXXXX.......................XXXX........X......... 17
cart_config2<3>      ..X.XXXXXXXXXXX.......................XXXX........X......... 17
blk5_bank<4>         ..XX.XXXXXXXXXX.......................XXXX........X......... 17
bank<2>              XX...............X..X..X..X..X..X..X......XXX..X............ 13
blk5_bank<3>         ..X.XXXXXXXXXXX.......................XXXX........X......... 17
blk3_bank<4>         ..XX.XXXXXXXXXX.......................XXXX........X......... 17
blk3_bank<3>         ..X.XXXXXXXXXXX.......................XXXX........X......... 17
bank<3>              XX................X.X...X.X...X.X...X.....XXX...X........... 13
blk2_bank<4>         ..XX.XXXXXXXXXX.......................XXXX........X......... 17
blk2_bank<3>         ..X.XXXXXXXXXXX.......................XXXX........X......... 17
blk1_bank<4>         ..XX.XXXXXXXXXX.......................XXXX........X......... 17
bank<4>              XX.................XX....XX....XX....X....XXX....X.......... 13
blk1_bank<3>         ..X.XXXXXXXXXXX.......................XXXX........X......... 17
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_SC$436 <= ((NOT blk5 AND ram1 AND ram3 AND ram2)
	OR (NOT blk3 AND ram1 AND NOT blk2 AND ram3 AND ram2));


$OpTx$ram_sel/ram_sel_D2_INV$819 <= (ram1 AND ram3 AND ram2);




bank(0) <= ((blk5_bank(0) AND $OpTx$FX_SC$436)
	OR (ram_bank(0) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (blk1_bank(0) AND blk5 AND blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2)
	OR (blk2_bank(0) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND 
	ram3 AND ram2)
	OR (blk3_bank(0) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2));


bank(1) <= ((blk5_bank(1) AND $OpTx$FX_SC$436)
	OR (ram_bank(1) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (blk1_bank(1) AND blk5 AND blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2)
	OR (blk2_bank(1) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND 
	ram3 AND ram2)
	OR (blk3_bank(1) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2));


bank(2) <= ((blk5_bank(2) AND $OpTx$FX_SC$436)
	OR (ram_bank(2) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (blk1_bank(2) AND blk5 AND blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2)
	OR (blk2_bank(2) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND 
	ram3 AND ram2)
	OR (blk3_bank(2) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2));


bank(3) <= ((blk5_bank(3) AND $OpTx$FX_SC$436)
	OR (ram_bank(3) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (blk1_bank(3) AND blk5 AND blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2)
	OR (blk2_bank(3) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND 
	ram3 AND ram2)
	OR (blk3_bank(3) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2));


bank(4) <= ((blk5_bank(4) AND $OpTx$FX_SC$436)
	OR (ram_bank(4) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (blk1_bank(4) AND blk5 AND blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2)
	OR (blk2_bank(4) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND 
	ram3 AND ram2)
	OR (blk3_bank(4) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2));


bank(5) <= ((blk5_bank(5) AND $OpTx$FX_SC$436)
	OR (ram_bank(5) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (blk1_bank(5) AND blk5 AND blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2)
	OR (blk2_bank(5) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND 
	ram3 AND ram2)
	OR (blk3_bank(5) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2));


bank(6) <= ((blk5_bank(6) AND $OpTx$FX_SC$436)
	OR (ram_bank(6) AND NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (blk1_bank(6) AND blk5 AND blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2)
	OR (blk2_bank(6) AND blk5 AND blk3 AND ram1 AND NOT blk2 AND 
	ram3 AND ram2)
	OR (blk3_bank(6) AND blk5 AND NOT blk3 AND ram1 AND blk2 AND 
	ram3 AND ram2));

FDCPE_blk1_bank0: FDCPE port map (blk1_bank(0),data(0).PIN,NOT clock,blk1_bank_CLR(0),'0',blk1_bank_CE(0));
blk1_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en);
blk1_bank_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk1_bank1: FDCPE port map (blk1_bank(1),data(1).PIN,NOT clock,blk1_bank_CLR(1),'0',blk1_bank_CE(1));
blk1_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en);
blk1_bank_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk1_bank2: FDCPE port map (blk1_bank(2),data(2).PIN,NOT clock,blk1_bank_CLR(2),'0',blk1_bank_CE(2));
blk1_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en);
blk1_bank_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk1_bank3: FDCPE port map (blk1_bank(3),data(3).PIN,NOT clock,blk1_bank_CLR(3),'0',blk1_bank_CE(3));
blk1_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en);
blk1_bank_CE(3) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk1_bank4: FDCPE port map (blk1_bank(4),data(4).PIN,NOT clock,blk1_bank_CLR(4),'0',blk1_bank_CE(4));
blk1_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en);
blk1_bank_CE(4) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk1_bank5: FDCPE port map (blk1_bank(5),data(5).PIN,NOT clock,blk1_bank_CLR(5),'0',blk1_bank_CE(5));
blk1_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en);
blk1_bank_CE(5) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk1_bank6: FDCPE port map (blk1_bank(6),data(6).PIN,NOT clock,blk1_bank_CLR(6),'0',blk1_bank_CE(6));
blk1_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en);
blk1_bank_CE(6) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk2_bank0: FDCPE port map (blk2_bank(0),data(0).PIN,NOT clock,blk2_bank_CLR(0),'0',blk2_bank_CE(0));
blk2_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en);
blk2_bank_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk2_bank1: FDCPE port map (blk2_bank(1),data(1).PIN,NOT clock,blk2_bank_CLR(1),'0',blk2_bank_CE(1));
blk2_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en);
blk2_bank_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk2_bank2: FDCPE port map (blk2_bank(2),data(2).PIN,NOT clock,blk2_bank_CLR(2),'0',blk2_bank_CE(2));
blk2_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en);
blk2_bank_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk2_bank3: FDCPE port map (blk2_bank(3),data(3).PIN,NOT clock,blk2_bank_CLR(3),'0',blk2_bank_CE(3));
blk2_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en);
blk2_bank_CE(3) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk2_bank4: FDCPE port map (blk2_bank(4),data(4).PIN,NOT clock,blk2_bank_CLR(4),'0',blk2_bank_CE(4));
blk2_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en);
blk2_bank_CE(4) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk2_bank5: FDCPE port map (blk2_bank(5),data(5).PIN,NOT clock,blk2_bank_CLR(5),'0',blk2_bank_CE(5));
blk2_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en);
blk2_bank_CE(5) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk2_bank6: FDCPE port map (blk2_bank(6),data(6).PIN,NOT clock,blk2_bank_CLR(6),'0',blk2_bank_CE(6));
blk2_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en);
blk2_bank_CE(6) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk3_bank0: FDCPE port map (blk3_bank(0),data(0).PIN,NOT clock,blk3_bank_CLR(0),'0',blk3_bank_CE(0));
blk3_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en);
blk3_bank_CE(0) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk3_bank1: FDCPE port map (blk3_bank(1),data(1).PIN,NOT clock,blk3_bank_CLR(1),'0',blk3_bank_CE(1));
blk3_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en);
blk3_bank_CE(1) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk3_bank2: FDCPE port map (blk3_bank(2),data(2).PIN,NOT clock,blk3_bank_CLR(2),'0',blk3_bank_CE(2));
blk3_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en);
blk3_bank_CE(2) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk3_bank3: FDCPE port map (blk3_bank(3),data(3).PIN,NOT clock,blk3_bank_CLR(3),'0',blk3_bank_CE(3));
blk3_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en);
blk3_bank_CE(3) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk3_bank4: FDCPE port map (blk3_bank(4),data(4).PIN,NOT clock,blk3_bank_CLR(4),'0',blk3_bank_CE(4));
blk3_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en);
blk3_bank_CE(4) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk3_bank5: FDCPE port map (blk3_bank(5),data(5).PIN,NOT clock,blk3_bank_CLR(5),'0',blk3_bank_CE(5));
blk3_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en);
blk3_bank_CE(5) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk3_bank6: FDCPE port map (blk3_bank(6),data(6).PIN,NOT clock,blk3_bank_CLR(6),'0',blk3_bank_CE(6));
blk3_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en);
blk3_bank_CE(6) <= (NOT r_w AND cart_en AND address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk5_bank0: FDCPE port map (blk5_bank(0),data(0).PIN,NOT clock,blk5_bank_CLR(0),'0',blk5_bank_CE(0));
blk5_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en);
blk5_bank_CE(0) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk5_bank1: FDCPE port map (blk5_bank(1),data(1).PIN,NOT clock,blk5_bank_CLR(1),'0',blk5_bank_CE(1));
blk5_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en);
blk5_bank_CE(1) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk5_bank2: FDCPE port map (blk5_bank(2),data(2).PIN,NOT clock,blk5_bank_CLR(2),'0',blk5_bank_CE(2));
blk5_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en);
blk5_bank_CE(2) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk5_bank3: FDCPE port map (blk5_bank(3),data(3).PIN,NOT clock,blk5_bank_CLR(3),'0',blk5_bank_CE(3));
blk5_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en);
blk5_bank_CE(3) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk5_bank4: FDCPE port map (blk5_bank(4),data(4).PIN,NOT clock,blk5_bank_CLR(4),'0',blk5_bank_CE(4));
blk5_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en);
blk5_bank_CE(4) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk5_bank5: FDCPE port map (blk5_bank(5),data(5).PIN,NOT clock,blk5_bank_CLR(5),'0',blk5_bank_CE(5));
blk5_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en);
blk5_bank_CE(5) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_blk5_bank6: FDCPE port map (blk5_bank(6),data(6).PIN,NOT clock,blk5_bank_CLR(6),'0',blk5_bank_CE(6));
blk5_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en);
blk5_bank_CE(6) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	address(2));

FDCPE_cart_config10: FDCPE port map (cart_config1(0),data(0).PIN,NOT clock,cart_config1_CLR(0),'0',cart_config1_CE(0));
cart_config1_CLR(0) <= (NOT reset.PIN AND NOT reset_en);
cart_config1_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config11: FDCPE port map (cart_config1(1),data(1).PIN,NOT clock,cart_config1_CLR(1),'0',cart_config1_CE(1));
cart_config1_CLR(1) <= (NOT reset.PIN AND NOT reset_en);
cart_config1_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config12: FDCPE port map (cart_config1(2),data(2).PIN,NOT clock,cart_config1_CLR(2),'0',cart_config1_CE(2));
cart_config1_CLR(2) <= (NOT reset.PIN AND NOT reset_en);
cart_config1_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config20: FDCPE port map (cart_config2(0),data(0).PIN,NOT clock,'0',cart_config2_PRE(0),cart_config2_CE(0));
cart_config2_PRE(0) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(0) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config21: FDCPE port map (cart_config2(1),data(1).PIN,NOT clock,cart_config2_CLR(1),'0',cart_config2_CE(1));
cart_config2_CLR(1) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(1) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config22: FDCPE port map (cart_config2(2),data(2).PIN,NOT clock,cart_config2_CLR(2),'0',cart_config2_CE(2));
cart_config2_CLR(2) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(2) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config23: FDCPE port map (cart_config2(3),data(3).PIN,NOT clock,cart_config2_CLR(3),'0',cart_config2_CE(3));
cart_config2_CLR(3) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(3) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config24: FDCPE port map (cart_config2(4),data(4).PIN,NOT clock,cart_config2_CLR(4),'0',cart_config2_CE(4));
cart_config2_CLR(4) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(4) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config25: FDCPE port map (cart_config2(5),data(5).PIN,NOT clock,cart_config2_CLR(5),'0',cart_config2_CE(5));
cart_config2_CLR(5) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(5) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config26: FDCPE port map (cart_config2(6),data(6).PIN,NOT clock,cart_config2_CLR(6),'0',cart_config2_CE(6));
cart_config2_CLR(6) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(6) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_cart_config27: FDCPE port map (cart_config2(7),data(7).PIN,NOT clock,cart_config2_CLR(7),'0',cart_config2_CE(7));
cart_config2_CLR(7) <= (NOT reset.PIN AND NOT reset_en);
cart_config2_CE(7) <= (NOT r_w AND cart_en AND NOT address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));


data_I(0) <= ((EXP6_.EXP)
	OR ($OpTx$ram_sel/ram_sel_D2_INV$819.EXP)
	OR (address(1) AND address(0) AND blk5_bank(0) AND 
	address(2))
	OR (NOT address(1) AND address(0) AND blk2_bank(0) AND 
	address(2))
	OR (NOT address(1) AND NOT address(0) AND cart_config1(0) AND 
	NOT address(2))
	OR (NOT address(1) AND NOT address(0) AND blk1_bank(0) AND 
	address(2)));
data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
data_OE(0) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


data_I(1) <= ((ram_bank(1).EXP)
	OR (blk1_bank(1).EXP)
	OR (address(1) AND address(0) AND blk5_bank(1) AND 
	address(2))
	OR (NOT address(1) AND address(0) AND blk2_bank(1) AND 
	address(2))
	OR (NOT address(1) AND NOT address(0) AND cart_config1(1) AND 
	NOT address(2))
	OR (NOT address(1) AND NOT address(0) AND blk1_bank(1) AND 
	address(2)));
data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
data_OE(1) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


data_I(2) <= ((cart_config2(1).EXP)
	OR (cart_config1(1).EXP)
	OR (address(1) AND address(0) AND ram_bank(2) AND 
	NOT address(2))
	OR (address(1) AND NOT address(0) AND blk3_bank(2) AND 
	address(2))
	OR (NOT address(1) AND address(0) AND cart_config2(2) AND 
	NOT address(2))
	OR (NOT address(1) AND address(0) AND blk2_bank(2) AND 
	address(2)));
data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
data_OE(2) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


data_I(3) <= ((blk5_bank(2).EXP)
	OR (address(1) AND address(0) AND ram_bank(3) AND 
	NOT address(2))
	OR (address(1) AND NOT address(0) AND blk3_bank(3) AND 
	address(2))
	OR (NOT address(1) AND address(0) AND cart_config2(3) AND 
	NOT address(2))
	OR (NOT address(1) AND address(0) AND blk2_bank(3) AND 
	address(2)));
data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
data_OE(3) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


data_I(4) <= ((blk5_bank(1).EXP)
	OR (address(1) AND address(0) AND ram_bank(4) AND 
	NOT address(2))
	OR (address(1) AND NOT address(0) AND blk3_bank(4) AND 
	address(2))
	OR (NOT address(1) AND address(0) AND cart_config2(4) AND 
	NOT address(2))
	OR (NOT address(1) AND address(0) AND blk2_bank(4) AND 
	address(2)));
data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
data_OE(4) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


data_I(5) <= ((blk3_bank(2).EXP)
	OR (address(1) AND address(0) AND ram_bank(5) AND 
	NOT address(2))
	OR (address(1) AND NOT address(0) AND blk3_bank(5) AND 
	address(2))
	OR (NOT address(1) AND address(0) AND cart_config2(5) AND 
	NOT address(2))
	OR (NOT address(1) AND address(0) AND blk2_bank(5) AND 
	address(2)));
data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
data_OE(5) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


data_I(6) <= ((ram_bank(6).EXP)
	OR (ram_bank(5).EXP)
	OR (address(1) AND address(0) AND ram_bank(6) AND 
	NOT address(2))
	OR (address(1) AND NOT address(0) AND blk3_bank(6) AND 
	address(2))
	OR (NOT address(1) AND address(0) AND cart_config2(6) AND 
	NOT address(2))
	OR (NOT address(1) AND address(0) AND blk2_bank(6) AND 
	address(2)));
data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
data_OE(6) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


data_I(7) <= (NOT address(1) AND address(0) AND cart_config2(7) AND 
	NOT address(2));
data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
data_OE(7) <= (r_w AND cart_en AND NOT io AND clock AND NOT cart_config1(2) AND 
	NOT address(5) AND NOT address(4) AND address(3) AND NOT address(9) AND 
	NOT address(8) AND NOT address(7) AND NOT address(6));


flash_ce <= NOT (((cart_config1(0) AND NOT cart_config1(1) AND 
	NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (cart_config2(0) AND NOT cart_config2(1) AND NOT blk1)
	OR (cart_config2(2) AND NOT cart_config2(3) AND NOT blk2)
	OR (cart_config2(4) AND NOT cart_config2(5) AND NOT blk3)
	OR (cart_config2(6) AND NOT cart_config2(7) AND NOT blk5)));


oe <= NOT ((r_w AND cart_en));

FDCPE_ram_bank0: FDCPE port map (ram_bank(0),data(0).PIN,NOT clock,ram_bank_CLR(0),'0',ram_bank_CE(0));
ram_bank_CLR(0) <= (NOT reset.PIN AND NOT reset_en);
ram_bank_CE(0) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_ram_bank1: FDCPE port map (ram_bank(1),data(1).PIN,NOT clock,ram_bank_CLR(1),'0',ram_bank_CE(1));
ram_bank_CLR(1) <= (NOT reset.PIN AND NOT reset_en);
ram_bank_CE(1) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_ram_bank2: FDCPE port map (ram_bank(2),data(2).PIN,NOT clock,ram_bank_CLR(2),'0',ram_bank_CE(2));
ram_bank_CLR(2) <= (NOT reset.PIN AND NOT reset_en);
ram_bank_CE(2) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_ram_bank3: FDCPE port map (ram_bank(3),data(3).PIN,NOT clock,ram_bank_CLR(3),'0',ram_bank_CE(3));
ram_bank_CLR(3) <= (NOT reset.PIN AND NOT reset_en);
ram_bank_CE(3) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_ram_bank4: FDCPE port map (ram_bank(4),data(4).PIN,NOT clock,ram_bank_CLR(4),'0',ram_bank_CE(4));
ram_bank_CLR(4) <= (NOT reset.PIN AND NOT reset_en);
ram_bank_CE(4) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_ram_bank5: FDCPE port map (ram_bank(5),data(5).PIN,NOT clock,ram_bank_CLR(5),'0',ram_bank_CE(5));
ram_bank_CLR(5) <= (NOT reset.PIN AND NOT reset_en);
ram_bank_CE(5) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));

FDCPE_ram_bank6: FDCPE port map (ram_bank(6),data(6).PIN,NOT clock,ram_bank_CLR(6),'0',ram_bank_CE(6));
ram_bank_CLR(6) <= (NOT reset.PIN AND NOT reset_en);
ram_bank_CE(6) <= (NOT r_w AND cart_en AND address(1) AND address(0) AND NOT io AND 
	NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND address(3) AND 
	NOT address(9) AND NOT address(8) AND NOT address(7) AND NOT address(6) AND 
	NOT address(2));


ram_ce <= NOT (((cart_config1(1) AND 
	NOT $OpTx$ram_sel/ram_sel_D2_INV$819)
	OR (cart_config2(1) AND NOT blk1)
	OR (cart_config2(3) AND NOT blk2)
	OR (cart_config2(5) AND NOT blk3)
	OR (cart_config2(7) AND NOT blk5)));


reset_I <= '0';
reset <= reset_I when reset_OE = '1' else 'Z';
reset_OE <= reset_en;

FDCPE_reset_en: FDCPE port map (reset_en,reset_en_D,NOT clock,'0','0');
reset_en_D <= (NOT r_w AND cart_en AND NOT address(1) AND NOT address(0) AND NOT io AND 
	data(7).PIN AND NOT cart_config1(2) AND NOT address(5) AND NOT address(4) AND 
	address(3) AND NOT address(9) AND NOT address(8) AND NOT address(7) AND 
	NOT address(6) AND NOT address(2));


we <= ((r_w)
	OR (NOT cart_en)
	OR (NOT cart_config1(0) AND NOT cart_config2(0) AND 
	NOT cart_config2(2) AND NOT cart_config2(4) AND NOT cart_config2(6)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-TQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13               XC9572XL-5-TQ100               63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 blk3                             51 VCC                           
  2 NC                               52 flash_ce                      
  3 KPR                              53 KPR                           
  4 KPR                              54 KPR                           
  5 VCC                              55 ram_ce                        
  6 r_w                              56 KPR                           
  7 NC                               57 VCC                           
  8 ram2                             58 KPR                           
  9 KPR                              59 KPR                           
 10 KPR                              60 KPR                           
 11 KPR                              61 KPR                           
 12 KPR                              62 GND                           
 13 KPR                              63 KPR                           
 14 KPR                              64 we                            
 15 data<3>                          65 KPR                           
 16 data<1>                          66 bank<2>                       
 17 data<4>                          67 bank<0>                       
 18 KPR                              68 bank<1>                       
 19 NC                               69 GND                           
 20 data<2>                          70 KPR                           
 21 GND                              71 KPR                           
 22 clock                            72 ram3                          
 23 KPR                              73 NC                            
 24 NC                               74 ram1                          
 25 KPR                              75 GND                           
 26 VCC                              76 io                            
 27 KPR                              77 cart_en                       
 28 data<5>                          78 blk5                          
 29 KPR                              79 blk2                          
 30 KPR                              80 NC                            
 31 GND                              81 blk1                          
 32 bank<5>                          82 address<8>                    
 33 KPR                              83 TDO                           
 34 NC                               84 GND                           
 35 data<0>                          85 bank<3>                       
 36 data<7>                          86 address<5>                    
 37 bank<6>                          87 address<3>                    
 38 VCC                              88 VCC                           
 39 oe                               89 address<1>                    
 40 KPR                              90 bank<4>                       
 41 reset                            91 data<6>                       
 42 KPR                              92 address<0>                    
 43 NC                               93 address<2>                    
 44 GND                              94 address<4>                    
 45 TDI                              95 address<6>                    
 46 NC                               96 address<7>                    
 47 TMS                              97 address<9>                    
 48 TCK                              98 VCC                           
 49 KPR                              99 KPR                           
 50 KPR                             100 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-TQ100
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 28
Pterm Limit                                 : 5