Timing Report

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Design Name UltiMem
Device, Speed (SpeedFile Version) XC9572XL, -10 (3.0)
Date Created Mon Dec 16 03:08:04 2013
Created By Timing Report Generator: version P.68d
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 9.000 ns.
Max. Clock Frequency (fSYSTEM) 111.111 MHz.
Limited by Clock Pulse Width for clock
Pad to Pad Delay (tPD) 11.000 ns.
Setup to Clock at the Pad (tSU) 6.500 ns.
Clock Pad to Output Pad Delay (tCO) 14.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 14.5 191 191
AUTO_TS_P2F 0.0 8.3 631 631
AUTO_TS_F2P 0.0 12.7 100 100


Constraint: TS1000

Description: PERIOD:PERIOD_clock:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clock to bank<0> 0.000 14.500 -14.500
clock to bank<1> 0.000 14.500 -14.500
clock to bank<2> 0.000 14.500 -14.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
address<0> to blk1_bank<0>.CE 0.000 8.300 -8.300
address<0> to blk1_bank<1>.CE 0.000 8.300 -8.300
address<0> to blk1_bank<2>.CE 0.000 8.300 -8.300


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
blk1_bank<0>.Q to bank<0> 0.000 12.700 -12.700
blk1_bank<1>.Q to bank<1> 0.000 12.700 -12.700
blk1_bank<2>.Q to bank<2> 0.000 12.700 -12.700



Number of constraints not met: 3

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
clock 111.111 Limited by Clock Pulse Width for clock

Setup/Hold Times for Clocks

Setup/Hold Times for Clock clock
Source Pad Setup to clk (edge) Hold to clk (edge)
address<0> 6.500 0.000
address<1> 6.500 0.000
address<2> 6.500 0.000
address<3> 6.500 0.000
address<4> 6.500 0.000
address<5> 6.500 0.000
address<6> 6.500 0.000
address<7> 6.500 0.000
address<8> 6.500 0.000
address<9> 6.500 0.000
cart_en 6.500 0.000
data<0> 6.500 0.000
data<1> 6.500 0.000
data<2> 6.500 0.000
data<3> 6.500 0.000
data<4> 6.500 0.000
data<5> 6.500 0.000
data<6> 6.500 0.000
data<7> 6.500 0.000
io<3> 6.500 0.000
r_w 6.500 0.000


Clock to Pad Timing

Clock clock to Pad
Destination Pad Clock (edge) to Pad
bank<0> 14.500
bank<1> 14.500
bank<2> 14.500
bank<3> 14.500
bank<4> 14.500
bank<5> 14.500
bank<6> 14.500
data<0> 14.500
data<1> 14.500
data<2> 14.500
data<3> 14.500
data<4> 14.500
data<5> 14.500
data<6> 14.500
flash_ce 14.500
ram_ce 14.500
data<7> 13.500
we 13.500


Clock to Setup Times for Clocks


Pad to Pad List

Source Pad Destination Pad Delay
address<0> data<0> 11.000
address<0> data<1> 11.000
address<0> data<2> 11.000
address<0> data<3> 11.000
address<0> data<4> 11.000
address<0> data<5> 11.000
address<0> data<6> 11.000
address<1> data<0> 11.000
address<1> data<1> 11.000
address<1> data<2> 11.000
address<1> data<3> 11.000
address<1> data<4> 11.000
address<1> data<5> 11.000
address<1> data<6> 11.000
address<2> data<0> 11.000
address<2> data<1> 11.000
address<2> data<2> 11.000
address<2> data<3> 11.000
address<2> data<4> 11.000
address<2> data<5> 11.000
address<2> data<6> 11.000
address<3> data<0> 11.000
address<3> data<1> 11.000
address<3> data<2> 11.000
address<3> data<3> 11.000
address<3> data<4> 11.000
address<3> data<5> 11.000
address<3> data<6> 11.000
address<3> data<7> 11.000
address<4> data<0> 11.000
address<4> data<1> 11.000
address<4> data<2> 11.000
address<4> data<3> 11.000
address<4> data<4> 11.000
address<4> data<5> 11.000
address<4> data<6> 11.000
address<4> data<7> 11.000
address<5> data<0> 11.000
address<5> data<1> 11.000
address<5> data<2> 11.000
address<5> data<3> 11.000
address<5> data<4> 11.000
address<5> data<5> 11.000
address<5> data<6> 11.000
address<5> data<7> 11.000
address<6> data<0> 11.000
address<6> data<1> 11.000
address<6> data<2> 11.000
address<6> data<3> 11.000
address<6> data<4> 11.000
address<6> data<5> 11.000
address<6> data<6> 11.000
address<6> data<7> 11.000
address<7> data<0> 11.000
address<7> data<1> 11.000
address<7> data<2> 11.000
address<7> data<3> 11.000
address<7> data<4> 11.000
address<7> data<5> 11.000
address<7> data<6> 11.000
address<7> data<7> 11.000
address<8> data<0> 11.000
address<8> data<1> 11.000
address<8> data<2> 11.000
address<8> data<3> 11.000
address<8> data<4> 11.000
address<8> data<5> 11.000
address<8> data<6> 11.000
address<8> data<7> 11.000
address<9> data<0> 11.000
address<9> data<1> 11.000
address<9> data<2> 11.000
address<9> data<3> 11.000
address<9> data<4> 11.000
address<9> data<5> 11.000
address<9> data<6> 11.000
address<9> data<7> 11.000
blk1 flash_ce 11.000
blk2 bank<0> 11.000
blk2 bank<1> 11.000
blk2 bank<2> 11.000
blk2 bank<3> 11.000
blk2 bank<4> 11.000
blk2 bank<5> 11.000
blk2 bank<6> 11.000
blk2 flash_ce 11.000
blk3 bank<0> 11.000
blk3 bank<1> 11.000
blk3 bank<2> 11.000
blk3 bank<3> 11.000
blk3 bank<4> 11.000
blk3 bank<5> 11.000
blk3 bank<6> 11.000
blk5 bank<0> 11.000
blk5 bank<1> 11.000
blk5 bank<2> 11.000
blk5 bank<3> 11.000
blk5 bank<4> 11.000
blk5 bank<5> 11.000
blk5 bank<6> 11.000
cart_en data<0> 11.000
cart_en data<1> 11.000
cart_en data<2> 11.000
cart_en data<3> 11.000
cart_en data<4> 11.000
cart_en data<5> 11.000
cart_en data<6> 11.000
cart_en data<7> 11.000
cart_en flash_ce 11.000
cart_en ram_ce 11.000
clock data<0> 11.000
clock data<1> 11.000
clock data<2> 11.000
clock data<3> 11.000
clock data<4> 11.000
clock data<5> 11.000
clock data<6> 11.000
clock data<7> 11.000
io<3> data<0> 11.000
io<3> data<1> 11.000
io<3> data<2> 11.000
io<3> data<3> 11.000
io<3> data<4> 11.000
io<3> data<5> 11.000
io<3> data<6> 11.000
io<3> data<7> 11.000
r_w data<0> 11.000
r_w data<1> 11.000
r_w data<2> 11.000
r_w data<3> 11.000
r_w data<4> 11.000
r_w data<5> 11.000
r_w data<6> 11.000
r_w data<7> 11.000
ram1 bank<0> 11.000
ram1 bank<1> 11.000
ram1 bank<2> 11.000
ram1 bank<3> 11.000
ram1 bank<4> 11.000
ram1 bank<5> 11.000
ram1 bank<6> 11.000
ram1 flash_ce 11.000
ram1 ram_ce 11.000
ram2 bank<0> 11.000
ram2 bank<1> 11.000
ram2 bank<2> 11.000
ram2 bank<3> 11.000
ram2 bank<4> 11.000
ram2 bank<5> 11.000
ram2 bank<6> 11.000
ram2 flash_ce 11.000
ram2 ram_ce 11.000
ram3 bank<0> 11.000
ram3 bank<1> 11.000
ram3 bank<2> 11.000
ram3 bank<3> 11.000
ram3 bank<4> 11.000
ram3 bank<5> 11.000
ram3 bank<6> 11.000
ram3 flash_ce 11.000
address<0> data<7> 10.000
address<1> data<7> 10.000
address<2> data<7> 10.000
blk1 ram_ce 10.000
blk2 ram_ce 10.000
blk3 flash_ce 10.000
blk3 ram_ce 10.000
blk5 flash_ce 10.000
blk5 ram_ce 10.000
cart_en we 10.000
r_w oe 10.000
r_w we 10.000
ram3 ram_ce 10.000



Number of paths analyzed: 922
Number of Timing errors: 922
Analysis Completed: Mon Dec 16 03:08:04 2013